A 10MS/s 16bit SAR ADC Achieving 100dB SFDR and 90dB SNDR in 0.18 um CMOS

This paper presents a 10MS/s 16bit ADC consisting of a 4 bit flash coarse ADC, a 14bit SAR fine ADC with 2 bit redundancy, that achieves nearly constant 90dB peak SNDR up to Nyquist and an SFDR of 100dB for Nyquist frequencies. The bottom-plate sampling with split-capacitor switching scheme eliminates CDAC’s sensitivity to parasitic capacitances on the top plates of the DAC as well as signal dependence of charge injection, while minimizing DAC switching energy without requiring a reference common mode (CM) voltage. In addition, a dynamic comparator with high gain and bandwitdth preamplifier achieves low noise and high speed operation. A foreground calibration method is implemented to correct capacitor DAC mismatch and reduce capacitor size, and the calibration is fully digital and doesn't require accurate references or input signals. At 10 MS/s, the ADC consumes 10 mW from a 1.8-V supply voltage in SMIC 0.18um CMOS process and achieves a Schreier figure of merit of 170.8dB.