Reliability Improvement by 0.153UM CMOS Using HDP-CVD at STI Edge Sin Liner

We investigated MOSFET shallow trench isolation (STI) process with SIN liner and found no “double hump” effect in the Id-Vg curves and solution leakage. Furthermore, the yield was good in the memory. In the STI corners, a sharp angle was jacked up by SIN. Although the yield result was very good, it was still a hidden danger and could affect GOX. We utilized the high-density plasma chemical vapor deposition (HDP-CVD) process to clip a certain number of SiN liners. From the experiment results, we found that SiN liner and sidewall oxidation significantly improved the time-dependent dielectric breakdown (TDDB).as a result of test, new technology does not generate hot carrier injection (HCI) effects.