A low-Power SRAM with charge cycling based read and write assist scheme

In a SRAM array, the largest power consumer is pre-charging or voltage switching on bit-lines in read or write operations. The paper presents a bit-line charge cycling based read and write assist circuit for static random-access memory. With help of the assist circuit, the BLs charges wasted in conventional design is reused for BLs pre-charging in next period. The proposed array is simulated in SMIC 14nm FinFET process with a supply voltage of 0.8V. Simulation results show that a 23%-43% power reduction is achieved compared with conventional designs.