Abstract:
This paper presents a next generation multi-objective co-optimization approach that enables the joint utilization of machine and human intelligence to address the growing...Show MoreMetadata
Abstract:
This paper presents a next generation multi-objective co-optimization approach that enables the joint utilization of machine and human intelligence to address the growing challenges in all stages of technology enablement. This approach is utilized in exploring optimal combinations of a rich set of design, technology and ingredients (DTI) to push the power/performance/area (PPA) envelope across sub-10nm derivatives of Intel technology nodes and various intellectual properties (IPs). It focuses on assisting design engineers in exploring the multi-faceted design space of ever-increasing complexity that is governed by convoluted trade-offs, which directly determine end product quality. This approach is applicable to all stages of the technology definition and readiness cycle. Here, a 10× improvement in turn-around time (TAT) with better quality of results (QoR) is reported compared to purely human-optimized high-performance CPU implementations in Intel’s 10nm technology node using various transistor, standard cell, metal stack, track pattern and methodology options.
Published in: 2019 IEEE International Electron Devices Meeting (IEDM)
Date of Conference: 07-11 December 2019
Date Added to IEEE Xplore: 13 February 2020
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