A Novel Digital Etch Technique for p-GaN Gate HEMT

We demonstrate the digital etching (DE) process to fabricated E-mode p-GaN/AIGaN/GaN HEMT. DE process comprising low power oxygen (02) plasma oxidizing and low power boron trichloride (BCl
₃
) plasma etching to selectively remove p-GaN layer. The atomic layer etching (ALE) has an etching rate of 1.62 nm/cycle to achieved depth of 70nm. The 5-μm source-drain offset length (L
_SD
) device with Ni/Au gate metal demonstrated 365 mAlmm drain current density with threshold voltage (V
_TH
) of +1.8V, on/off current ratio of 1.6×10
⁶
, breakdown voltage (BV) of 154V, and static on-resistance (R
_ON
) of 8.47 Ω.mm. The 20-μm L
_SD
device with Ni/Au gate metal demonstrated 211 mA/mm drain current density with V
_TH
of +2V, and on/off current ratio of 1. 2×10
⁶
, BV of 426V, and static R
_ON
of 17.3 Ω.mm.