A 0.5 /spl mu/m 3 V 1T1C 1 Mb FRAM with a variable reference bitline voltage scheme using a fatigue-free reference capacitor

Ferroelectric random access memory (FRAM/sup (R)/) has been intensively studied because of its high potential for low-power, high-speed operation and high switching endurance. The 2-transistor 2-capacitor (2T2C) cell structure offers stable read, however, it is not suitable for a high-density memory because of the larger cell area. The 1-transistor 1-capacitor (1T1C) cell structure is expected to be the key technology for realizing a megabit FRAM.