Thermal performance evaluation of dual-side cooling for a three-dimensional (3D) chip stack: Additional cooling from the laminate (substrate) side

When a 3D chip stack is composed of some memories and a logic device such as processor, the logic device has been assumed to be located as a bottom chip in wide I/O and HBM applications. On the other hand, for high-end server applications, a processor needs to be located as a top chip because it needs to be cooled efficiently. In this case, many Through Silicon Vias (TSVs) are necessary in a memory (bottom chip), because a processor (top chip) requires many electrical connections (power, ground, signal) with a substrate [1]. However, when effective cooling from the bottom side of chips ( from the substrate side) is achieved, a processor can be located as a bottom chip, and only a small numbers of TSVs are required in a processor which electrically connects a memory and a substrate [2,3].In this paper, we will describe how to realize effective cooling from the bottom side of chips, assuming a laminate, which consists of organic dielectric materials and copper, as substrate. A 3D package for high-end server applications is assumed to be composed of a top and bottom side heat-sinks, thermal interface material-2 (TIM-2) between a top side heat-sink and a heatspreader, a heat-spreader (lid), TIM-1 between a heat-spreader and stacked chips, stacked chips, a laminate and a mother board. For effective cooling from the bottom side of chips, the distance between a bottom chip and a bottom side heat-sink should be shortened. Therefore, the following three structural improvements are proposed. Firstly, re-distribution layers (RDL) by wafer level packaging (RDL-first process) is adopted to shorten the thickness of the wiring layer (there is no laminates). Secondly, a mother board is drilled and a bottom side heat-sink is embedded in the drilled cavity, where a few layers of circuits (wiring) are kept in a mother board for electrical connections. Thirdly, the joint (interconnection) between a bottom chip and RDL, and also the joint between RDL and a mother board are shortened as short as possible (for example, the joint height of 25μm is preferable). In addition to the short distance between a bottom chip and a bottom side heat-sink, high thermal conductivity material should be used between a bottom chip and a bottom side heat-sink. First exampleis underfill in the joint layer. Underfill occupies a large area of the joint layer, such as 80%, therefore its thermal conductivity significantly affects the thermal resistance of the joint layer [4]. Underfill of 1.5-2 W/mK is desirable. To realize effective cooling from the bottom side of chips, the requirements for each item are discussed qualitatively. We perform thermal conductivity measurements of each component, such as joint, and based on these measured thermal conductivities, we also demonstrate how much thermal resistance is achieved by cooling from the bottom side of chips. It is clarified that the maximum allowable heat density of a bottom chip is 24.5 W/cm2, and it is shown that by further thickness reduction of each component, 44.0 W/cm2 is realized.