A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS

This letter presents a 0.32 pJ/bit 100-Gb/s PAM-4 CMOS transimpedance amplifier (TIA). Several techniques are proposed to alleviate TIA design tradeoffs while pushing energy efficiency to a limit. A multipeaking input network is designed to relieve the bandwidth (BW) degradation from parasitics of input interface and ESD diodes. An inverter-based single-ended continuous-time linear equalizer (CTLE) enhanced with a Q-shaping inductor is used to further extend the BW. Moreover, a current reuse variable gain amplifier (VGA) based on a transadmittance stage (TAS)-transimpedance stage (TAS-TIS) topology is proposed to provide a dynamic range of 9 dB while maintaining the overall BW and linearity. Implemented in 28-nm CMOS, the TIA achieves a 28-GHz BW with a 65 dB $\Omega $ dc transimpedance, while showing an input referred noise density of 16 pA/ $\surd $ Hz and a total harmonic distortion (THD) < 5% up to $640~\mu $ App input current. The TIA consumes 32 mW from a 1.2-V supply, achieving superior BW and energy efficiency among 100-Gb/s+ CMOS TIA designs.