Evaluation of Threshold Hysteresis for SiC MOSFETs in Active Gate Drive Application

The threshold hysteresis of silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOS-FETs) has garnered significant interest. Nevertheless, limited research has concentrated on the threshold hysteresis of SiC MOSFETs during active gate drive (AGD) application. This paper systematically analyzes the switching performance of threshold hysteresis at different switching rates and gate voltages via the interface electric field. The analysis indicates that an increase in gate negative voltage and turn-on speed correlates with elevated starting values and hysteresis of the interface state hole trap, resulting in an increase in interface trap current inside the drive loop and a quicker turn-on speed of SiC MOSFETs. Different gate structures 1200 V SiC MOSFETs are assessed utilizing a current source AGD. The test findings indicate that the turn-off performance of SiC MOSFETs is unaffected by variations in gate positive voltage. Nonetheless, an increase in gate negative voltage and turn-on speed correlates with a greater proportion of turn-on speed attributable to threshold hysteresis. In high-speed operational mode, the threshold hysteresis proportion in turn-on loss reaches 36.7 %, with a peak crosstalk voltage maximum of 5.87 V. This study offers theoretical assistance for the AGD design of SiC MOSFETs in high-speed circuits or crosstalk voltage mitigation strategies.