Intermetallic Compounds (IMCs) Growth Investigation, Kinetic Parameter Analysis and Reliability Evaluation of In Solder Metal for 3D Integration Packaging

The increasing demand for higher functional density in microelectronics necessitates the miniaturization of interconnects in 3D integration, which presents challenges in processing and reliability. During fabrication and service life, interconnect microbumps remain in a non-equilibrium state, leading to interfacial reactions and atomic diffusion that drive intermetallic compounds (IMCs) growth and phase transformations, impacting the electrical, thermal, and mechanical properties, and affecting long-term reliability. With global restrictions on Pb-based solders, indium (In) has emerged as a viable low-melting-point alternative, especially for temperature-sensitive packaging. Understanding IMCs kinetics in In-based systems is essential for optimizing reliability. This study investigates the kinetics and phase transformation of IMCs in Ni/In and Cu/In systems under solid-state aging conditions using an in-situ resistance measurement technique. The approach overcomes the limitations of traditional scanning electron microscopy (SEM)-based analysis by enabling continuous monitoring of IMCs growth. The Ni/In system forms Ni₃In₇ through a reaction-controlled mechanism with an activation energy of $108~\pm ~30$ kJ/mol. In the Cu/In system, CuIn₂ is formed at room temperature that undergoes a phase transformation to Cu₁₁In₉ via a peritectoid reaction above $107.5~^{\circ }$ C of iso-thermal aging. The transformation shifts from a reaction-diffusion mixed controlled regime at $110~^{\circ }$ C (n $\approx ~0.73$ ) to diffusion control between 120- $140~^{\circ }$ C (n $\approx ~0.45$ –0.62), and possibly to grain-boundary diffusion at $150~^{\circ }$ C (n $\approx ~0.19$ ). The activation energy for CuIn ${}_{2} \to $ Cu₁₁In₉ transformation is $196~\pm ~82$ kJ/mol, indicating a higher energy barrier. These findings contribute to the development of low-temperature bonding techniques and fine-pitch interconnect optimization for future microelectronics packaging.