A 2.06-zFrms Resolution Lock-In Amplifier With SAR-Assisted Parasitic and Baseline Capacitance Compensation

This article presents the design and implementation of a precision lock-in amplifier for universal capacitive sensing. While conventional capacitive transimpedance amplifier (C-TIA) based on lock-in detection can extract subtle capacitance changes from a noisy environment, the capacitance resolution is further limited by parasitic capacitance at the input node, the baseline capacitance of the sensor, and current noise introduced by input bias resistor. To address these limitations, this work proposes a zeptofarad (zF) resolution lock-in amplifier using three key techniques: 1) a self-calibrated negative capacitor (NC) to cancel the parasitic capacitance at C-TIA input; 2) baseline capacitance compensation to improve the dynamic range (DR), allowing the use of higher excitation voltages, thereby improving the SNR; and 3) multi-element pseudo-resistor (PR) to mitigate shot noise in the presence of elevated input dc current. The proposed lock-in amplifier was implemented in a standard 180-nm CMOS process, achieving a best-in-class resolution of 2.06 zF ${}_{\mathbf {rms}}$ (BW = 10 Hz) while tolerating a maximum input dc current of 122 nA. This amplifier enables wideband lock-in detection from 1 kHz to 62 MHz. Both parasitic and baseline capacitance can be automatically calibrated in the foreground, considerably improving the speed and practicality of the measurement.