A SHA-Less Front-end Stage Structure Suitable for Time-Interleaved Pipeline ADC

This paper proposes a sample-and-hold amplifier (SHA)-less front-end stage structure suitable for pipeline ADCs in time-interleaving architecture with large interleaving factor. A low resolution SARADC is adopted as the sub-quantizer, and a bridge capacitor is introduced to connect the two capacitor arrays of the MDAC and the sub-ADC. Compared to commonly used pipelined-SAR ADC architectures, the proposed front-end stage structure reduces the reference load on the sub-quantizer during coarse conversion, while preserving the benefits of a shared sampling network in the sampling process. A 14-bit 500-MS/s pipeline ADC channel in an 8-way time-interleaved architecture utilizing the proposed front-end stage structure is designed in 28-nm CMOS process. Simulation results well demonstrate that the proposed front-end stage structure is highly immune to aperture errors, and shows the ADC channel achieves 69.13 dB SNDR and 83.8 dB SFDR at Nyquist frequency. With an estimated power consumption of 40-mW, a Walden FoM of 34.24-fJ/conv.-step is achieved.