The Study and Challenges of Backside Metal Interface Material to Enhance Fan-Out Embedded Bridge Die Package (FO-EB) Thermal Performance

Fan-out package with localized silicon interconnection using embedded bridge dies (FO-EB) have been developed for high performance computing (HPC). The typical FO-EB package is integrated advanced silicon node devices with multiple high band-width memory packages or chiplets bridged by local silicon dies, thus higher power consumption is expected for the advanced multi-dice systems. Indium metal is one of the possible thermal interface materials (TIM) to provide high thermal conductivity (>80W/mK) that have been used in high-end Flip Chip Package. However, it is limited reported to discuss indium metal TIM integrated in lidded FO-EB package. The challenges of indium TIM integrated into FO-EB package include the optimization of wafer level metal stack-up structure & process on backside of molded chip module wafers and subsequent on substrate assembly to integrated indium TIM with heat sink to achieve higher thermal dissipation. In this investigation, the backside metal stack-up performance across molding compound and silicon die area on chip module wafers are compared and two different backside metal stack-up structures are also analyzed. The FO-EB package size is ~5700 mm^2, two TV1 dies and eight TV2 dies connected by ten bridge dies are integrated in the fan-out package. The chip module warpage behavior & optimization before backside metal deposition is studied and the backside metal adhesion, deposition uniformity across the molded chip module wafers is also collected & analyzed. After completing package assembly, the samples were submitted to package reliability test to verify the qualities of backside metal with indium TIM. The goal of this investigation is to demonstrate backside metal stack-up performance on FO-EB chip module and robust interconnection with indium TIM to meet future high-end HPC requirements.