Embedded cooling to meet the 2kW thermal design power of HPC chips in the future

The rapid development of large models like GPT-4 has led to a significant increase in demand for high performance computing. This surge in transistor density has result in heat generation surpassing kW levels, necessitating more efficient heat dissipation methods. In this paper, a silicon-based staggered strip fin manifold embedded cooling scheme for high-performance computing chips is proposed. The top slit and bottom microchannel wafers are etched on two silicon wafers, and thereafter assembled employing the Cu-Sn bonding process, finally bonded to manifold to form the cooling vehicle. Copper serpentine resistors are prepared for heating and an infrared camera is utilized to observe the global temperature. Under a heat power of 1150 W, the average temperature rise is 34.6 °C, the thermal resistance is 10.8 mm²K/W when using deionized water as the coolant at the volume flow rate and pressure drop of 1 L/min and 13.5 kPa, respectively. The thermal resistance agreed with the simulation results within 1.5 mm²K/W. Consequently, at a temperature rise of 60 °C and a flow rate of 1 L/min, a total power of 2000 W will be effectively dissipated.