Temperature Gradient Control and Packaging Technologies for Co-Packaged Optics

As the demand for computing power driven by generative artificial intelligence continues to increase, the need for data transfer and communication between different components of AI systems is also constantly rising. However, the traditional electrical I/O combined with pluggable optical modules fail to meet the application demands in terms of bandwidth, cost, and power consumption. Co-packaged optics (CPO) is widely regarded as a key solution and development trend for future data center optical interconnects. By integrating Photonic integrated circuits (PICs) and electronic integrated circuits (EIC) on a shared substrate, the CPO solution provides shorter electrical interconnection length, higher bandwidth and energy efficiency. The main challenge in CPO is the susceptibility of optical chips to high temperatures, leading to thermal fragility. Optical chips commonly feature fiber pigtail fixed with UV adhesive and DFB lasers employing flip-chip configuration, both vulnerable to high-temperature packaging processes. The packaging temperature is usually required to be below 100°C, which is incompatible with high-temperature processes such as reflow soldering used for electronic chips packaging. In this work, we propose an low temperature Co-packaged technique. The Application-Specific Integrated Circuit (ASIC) chips and optical engine were packaged on a substrate, achieving a PAM-4 transmission of $4\times 50\ \text{Gbps}$. The measured bit error rate of the receiver is less than $2\times 10^{-4}$, when the input optical power is -13 dBm. We believe that this research provides a significant solution for researchers in the fields of optical communication and data centers, accelerating industry development.