A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction

A 2-read/write (2RW) pseudo dual-port (PDP) 6T SRAM is developed on 3nm Fin-FET technology. To improve performance, high-R wire tracking is introduced to adjust between margin, obtaining the optimum speed over various sign-off conditions. In addition, to reduce the dynamic power, the pre-charge control circuits are newly proposed to be aware of the 1^st and 2^nd sequential accesses. Meaningless bitline pre-charges for the 2^nd access are eliminated in either all columns or se lected columns, reducing the dynamic power in bitlines by up to 43 %. The fabricated 288-kbit 2RW PDP SRAM macro achieves the highest world record of 19.87 Mbit/mm² bit-density thanks to PDP design.