A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces

This paper presents a 20Gb/s/pin single-ended PAM-4 transceiver with advanced switching jitter compensation (SWJC) technique. The SWJC operates independently of equalization, hence further improving timing margin from 0.26UI to 0.39UI at a Ie-I2 BER. The proposed pre-channel SWJC at a transmitter side minimizes switching jitter (SWJ) of middle eye, modulating the transitions of top and bottom eyes in a beneficial way for SWJC at a receiver side. Ultimately, along with the proposed SWJC technique, the timing margins improved by SWJC at a receiver side are further increased, having overheads only 1.6% in power and 0.22% in area.