The Application of MUX in the Realming of Domino Logic, Dynamic Consequently, and Transmission Gates: A Case Study with Performance Calculation

One of the most crucial elements of communication networks are multiplexers (MUX). An effective low power-delay MUX architecture is needed to boost data transmission efficiency, effectively use a computer's enormous memory, and convert parallel data into serial form in telecommunication networks. Thus, a basic 4:1 MUX is created using a variety of CMOS logic families, including static CMOS logic, pseudo-NMOS logic, Domino logic, dynamic logic, multiplexers using a transmission gate, and dual-rail Domino logic, to determine the best suitable logic family for creating higher levels of MUX. VLSI technology is used for implementation, as it has features like small size, low cost, high operating speed, and low power. Using a VLSI back-hand tool, Cadence VIRTUOSO SCHEMATIC EDITOR 6.1 at 180nm, the performance analysis of the MUX using various CMOS logic families is carried out. A 4:1 MUX based on Domino logic is found to be the most effective based on the results. Its PDP (power delay product) is 20.1% lower than that of other logic families, and its average power consumption is 20.06%. But trade-offs are inferred between Domino logic and static CMOS logic, which can be neglected when considering overall performance. This work suggests that any higher-level MUX with low power-delay and PDP can be achieved using Domino logic as it outperforms the other logic families.