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A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads | IEEE Journals & Magazine | IEEE Xplore

A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads


Abstract:

With the scaling down of the transistor technology, intrinsic gains of the devices are continuously dropping. Meanwhile, high-gain operational transconductance amplifiers...Show More

Abstract:

With the scaling down of the transistor technology, intrinsic gains of the devices are continuously dropping. Meanwhile, high-gain operational transconductance amplifiers (OTAs) using technologies with reduced feature sizes are required in various applications. This article presents a 55-nm-fabricated three-stage OTA with a single cascode Miller capacitor for driving large capacitive loads. To achieve a high dc gain, a gain enhancement (GE) circuit is used in the first stage to boost the overall voltage gain to above 100 dB. To obtain a stable frequency response, a cascode Miller compensation scheme together with the GE circuits are used to push the nondominant complex pole to higher frequency and adjust the Q -factor. The proposed three-stage OTA is implemented in a 55-nm low-power (LP) CMOS process and occupies an area of 0.005 mm2. A current consumption of 157 \mu \text{A} can be measured with a supply voltage of 1.2 V. The measured results show that this three-stage OTA can achieve stable frequency and transient step responses when driving 2.5-to-30-nF capacitive loads. With a 15-nF capacitive load, a gain bandwidth (GBW) of 0.82 MHz, a phase margin (PM) of 53°, an average slew rate of 0.13 V/ \mu \text{s} , and an average 1% settling time of 2.62 \mu \text{s} can be achieved.
Page(s): 1970 - 1979
Date of Publication: 25 October 2023

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