Design of Low-offset and High-speed CTLE Cell based on 65 nm Process

Based on the SMIC 65nm CMOS process, a high-speed continuous-time linear equalization (CTLE) with the proposed direct-current offset cancellation (DCOC) circuit is designed, error amplifier-capacitor filter and current adder are added basing on the traditional DCOC circuit, which improves offset cancellation ability under ensuring stability. Mean value of the offset voltage at output is suppressed to 17 μV with 1.1 mV standard deviation. Operating at 1.2V power supply, the design achieves 7 GHz bandwidth with 4.7 dB peak gain, 51 dB loop gain, 72 ° phase margin, -52 dB DC gain and 1.9 mW power consumption, DCOC circuit only contributes 0.1 mW.