A Comparison Study of Spin-Transfer Torque- and Spin-Orbit Torque-Based Stochastic Computing Using Computational Random Access Memory (SC-CRAM)

Stochastic computing (SC) is a computing method that benefits from high noise resiliency and can perform complex arithmetic functions with a small number of logic gates, thus making it a promising solution for next generation neuromorphic systems. However, generating random bit-streams using CMOS-based technologies requires a large number of transistors, thus drastically increasing the total computation delay and energy consumption. In our previous work, we presented a solution where stochastic computation and stochastic bit generation were embedded within the same memory cell using a spintronic-based in-memory computing architecture called computational random access memory (CRAM), which we called SC-CRAM. In this work, we evaluate and compare the performance of SC-CRAM between spin-transfer torque (STT) and spin-orbit torque (SOT) switching mechanisms using key parameters of magnetic tunnel junctions (MTJs) from the research laboratories, the current industry standards, and the project performance metrics. Our calculations showed that, based on current trends, the performance of SC-CRAM can be further optimized by utilizing the SOT switching mechanism when the tunneling magnetoresistance (TMR) ratio of the MTJ pillars increases and the resistance-area (RA) product of the pillars is minimized. SC-CRAM benefits from high noise resilience and small array sizes, and our results demonstrate that its performance metrics can be enhanced.