Design and Development of Low Power and Area Efficient Design for VLSI Circuits

The term Very Large-Scale Integration (VLSI) refers to an Integrated Circuit (IC) type that uses countless transistor connections on a small chip. Arithmetic Logic Unit (ALU) design is crucial for both low power consumption and excellent performance as the ALU is a crucial component for mathematical and computational activities. Leakage power uses up a considerable amount of the overall energy as process technologies develop from one generation to the next. In both standby and active modes, there are many techniques to reduce leakage power. Input Vector Control (IVC), a non-process technology approach that relies on the transistor stacking effect, is one such technique. In standby mode, it reduces leakage power. A search technique called the Gravitational Search Technique (GSA) is used to find the Minimum Leakage Vector (MLV). Using the PSPICE tool and several test circuits, 16-bit and 32-bit ALUs are developed in this research. Verilog HDL is used for the coding, and the Xilinx vivado platform is used for simulation and synthesising these coded designs. Comparative study has demonstrated that GSA outperforms Genetic Algorithm in terms of iterations and low leakage power.