Design and Implementation of Low Power Posit Arithmetic Unit for Efficient Hardware Accelerators

There is an increasing interest in hardware accelerators, both in academia and industry. The industry invests in application-level accelerators, like Graphics Processing Units (GPUs) or Field programmable Gate Array (FPGA) accelerators connected to the PCIe bus. Hardware accelerators outperform general purpose Central Processing Units (CPUs) in terms of power consumption and performance. Hardware accelerators seek to optimize arithmetic operations, since it is the heart of the computation circuitry in different algorithms and applications. In this context, posit is proposed to replace IEEE Standard 754-2008 floating point and offers more efficient arithmetic units in terms of accuracy and Power-Performance-Area (PPA) matrix. In this paper, we introduce a low power Verilog HDL design and implementation of Posit Arithmetic Unit (PAU) for efficient hardware accelerators. Our regular proposed PAU is synthesized on Xilinx ZYNQ-7000. The results show34% area improvement and 14% power saving, while our compact PAU achieves 25% area reduction and 45% power saving.