FPGAs and fault tolerance

In this paper we propose a modification of the standard structure of FPGA configuration memory cells in the torus structure. The proposed modification gives the FPGA the ability to shift the configuration data inside the chip as a torus structure. We show that FPGAs having this ability give better results in terms of test, diagnosis and defect/fault tolerance. Only faults occurring in configurable logic blocks are considered in this paper. Testing and diagnosing faults in the chips having the proposed modification are achieved by loading typically only one set of configuration data. The other configuration data required for test and diagnosis are obtained by shifting the first set inside the chip. This makes test and diagnosis faster. Our simulation results show that this way of testing is especially effective when the complexity of the configurable logic blocks or the size increases. On the other hand, the defect tolerance is transparent to the user and is achieved with a very high yield, while the fault tolerance is achieved on chip with the original user configuration data and without hardware intervention. Additionally, using 0.5 /spl mu/m technology, we have designed and manufactured a prototype of an FPGA similar to the Xilinx 4000 series structure having the ability to shift data.