A linear MOS transconductor using source degeneration and adaptive biasing

This paper presents a new configuration for linear MOS voltage-to-current conversion (transconductance). The proposed circuit combines two previously reported linearization methods. The topology achieves 60-dB linearity for a fully balanced input dynamic range up to 1 V/sub pp/ at a 3.3-V supply voltage, with slightly decreasing performance in the unbalanced case. The linearity is preserved during the tuning process for a moderate range of transconductance values. The approach is validated by both computer simulations and experiments.