On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model

Embedded cores are being increasingly used in the design of large System-on-a-Chip. Because of the high complexity of SoC, the design verification is a challenge for system integrator To reduce the verification complexity, the port order fault model proposed by Tung and Jou (1998) has been used for verifying core-based designs and the corresponding verification pattern generation have been developed. Adders and multipliers are the most often used data path elements in core-based designs. Due to their regularity, the development of the verification pattern sets can be achieved in a systematic method. In this paper, we present the algorithms of generating the minimum verification pattern sets for adders and multipliers and these pattern sets are much smaller than that obtained from the automatic verification pattern generation proposed by Wang, Tung and Jou (2001).