A 585mV, 16.6fJ/cycle, 0.2μW Variation Tolerant Scannable Hybrid Flip-Flop in 65nm CMOS LSTP

In this paper, we propose a novel hybrid scannable flip-flop which can operate at near-threshold and conventional supply voltages. The proposed design improves t
dq
delay by 39% and static power dissipation by 59% at 0.585V when compared to the transmission gate based master slave flip-flop in 65nm Low Standby Power (LSTP) technology. It consumes 208nW power at 25% data activity and 16.6fJ/cycle at 50MHz during active operation and has a power-delay product of 0.98fJ. The performance and power improvements are brought about by a 15% loss in area which is an acceptable tradeoff in low power performance intensive systems. The proposed design also enables time borrowing, thus averaging out data path variations which can cause failures at low supply voltages.