Solder Void Improvement Beyond Process Flow

In current SiP (System in Package) products, some solder voids in BTC (Bottom terminal Component) solder joints are usually out of USI specification, and even cause bridge after additional reflows. The solder void reduction is increasingly important to improve soldering quality and yield. The most effective way to solve solder void issue is to use vacuum reflow oven in SMT (Surface mounted Technology). However, the price of vacuum reflow oven is at least four times that of common reflow oven. Therefore, it is necessary to develop a way that is more cost-effective. This study started from parameter modification without process change. No matter optimizing the reflow profile or increasing the stencil aperture, the number of solder voids did not decrease. Therefore, process change was considered in the second phase, aiming to get a good void improvement. After baking for 20 minutes before going through SMT reflow, the solvent in solder paste volatilized well and the void % was reduced by around 20%, which makes solder voids within USI specification. The incorporation of this method in HVM will lead to process flow change, since an additional common reflow oven is needed for prebaking before SMT reflow. Nevertheless, the cost saving can be at least 50% comparing with the vacuum reflow oven.