Suppression of series parasitic resistance and observation of quantum effects in a silicon single-electron transistor

We have fabricated a silicon point-contact channel SET with low series resistance using VLSI-compatible process. By narrowing only the point-contact region and suppressing the series parasitic resistance, the peak conductance as large as 8.8 /spl mu/S and the silicon quantum dot as small as 7.6 nm are simultaneously obtained. Current staircase due to the large quantum level spacing is clearly observed at low temperatures. From numerical calculations, it is found that the staircase feature due to discrete quantum levels stands out even at room temperature in future silicon SETs with an ultra-small dot.