Differential-voltage attenuator based on floating-gate MOS transistors and its applications

In this brief, a very simple differential voltage attenuator based on floating-gate MOS transistors (FGMOS) is proposed. The attenuator constructed by only two stacked identical FGMOS in saturation region, provides a voltage output proportional to the difference of the two input voltages. The advantages of this attenuator are the low supply operation, the rail-to-rail input range with small linearity error and the single-ended input processing. A very efficient technique to transform any circuit that requires only balanced inputs into the single-ended counterpart based on the attenuator, is proposed. Using this technique, a number of single-ended computational circuits are produced such as voltage squarer, four-quadrant multiplier, and vector summation circuit. The circuits can be fabricated in standard double-poly, double-metal CMOS technology and they are suitable for analogue signal processing and neural networks applications. SPICE simulation results using 2-/spl mu/m MIETEC CMOS process parameters demonstrate the feasibility and the accuracy of the circuits.