Execution-driven simulation of IP router architectures

A number of approaches have been proposed by different vendors for the next generation Internet router architectures, capable of processing millions of packets per second. Most of this processing speed stems from employing latest high-performance network processor or multiprocessors as the forwarding engine of the router However, all these improvements have been proposed without any detailed study in performance evaluation. The impact of instruction level parallelism, branch prediction, multiprocessing, and cache architectures on the performance of routers is not known. In the paper a methodology is proposed, which extends an execution-driven simulator to evaluate router architectures. We incorporate the exact model of an IP router into RSIM to analyze its performance and also develop a framework for feeding real Internet traces to the simulator Our work enables us to vary system parameters to simulate and analyze designs of realistic system with a range of traces. It is shown that the performance of Internet routers can be dramatically enhanced by using multiprocessor architectures. The router design also considers various cache replacement policies and router arbitration policies.