TCAD challenges and opportunities to find a feasible device architecture for sub-3nm scaling

With the aggressive scaling of MOSFET devices below 3nm, the role of TCAD in selecting a feasible device architecture for next node has become extremely important. There is an enormous opportunity cost for each choice, so the pros and cons of each option must be identified through seamless pre-validation using TCAD. Therefore, it is important to understand which TCAD solutions are necessary to validate the architecture candidate in rigorous way. This paper describes which TCAD solutions are important in atomic/device/standard cell/block-chip level for next generation logic pathfinding from the perspective view of a semiconductor manufacturing industry.