FCCSP(MUF) Mold-flow Void Risk Prediction with Different Substrate Surface and Bump Height Design

Today's flip chip scale packaging (FCCSP) microelectronics products are becoming more and more complex, especially in the packaging process using molded underfill manufacturing, which reduces the cost of flip chip technology such as molded underfill (MUF) High, provides molding ability in molding. The problem is to leave effective space under the chip. Generally speaking, this requires a lot of experimental DOE (chip size, substrate design, and epoxy resin type) to solve this problem. For the reasons mentioned above, mold-flow simulation software can be applied to use different flow condition to obtain the best solution as the MUF FCCSP of the substrate structure design. Such a simulation method can help shorten the product development cycle. This article uses the commonly used 3D molding process simulation software for transferring manufacturing process parameters. This article will introduce a comparison of two different structures. A MUF is FCCSP, it is matched with different bump height (SOH) structure comparison (control the flow of different chip bottom space), and observe the difference of the flow melt-front. The second is that there are two different designs on the surface of the substrate (welding masks with completely open or partially open patterns) through the table to enter the previously separated welding mask samples (welding masks with l0um depth structure) to maintain different modes. As this research, we can get a lot of conclusion that improve the molding capability of molded underfill FCCSP in the transfer molding process. If the bottom of the molded underfill FCCSP chip is matched with a structure with a height of 55 µm, then the molding epoxy can easily flow under the area with a large flow space, so the risk of entrapment can be reduced. In addition, the molding compound also has good melt front fluidity, and the fully open substrate surface design of the substrate solder resist layer can achieve more l0µmm space underneath the die area. Then, the CAE output are consistent as the experiment and it can to predict whether the product has a risk assessment of void.