A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop

This article presents a wide-lock-in-range and ultralow-jitter, 12–14.5 GHz subsampling phase-locked loop (SSPLL) using a frequency-disturbance-detecting/correcting (FDC) loop. By detecting and correcting the frequency disturbance,
$f_{\mathbf {D}}$
, frequently, the FDC loop can increase the lock-in range of the SSPLL to 3.2 times the reference frequency,
$f_{\mathbf {REF}}$
. Since the FDC loop only is concerned with correcting an
$f_{\mathbf {D}}$
-event at the output and is not concerned with the jitter, there is no design tradeoff between the jitter, and the power consumption as is the case in previous techniques. Due to its logic using frequency information rather than phase, the FDC loop also can reduce the time required for the reacquisition of the frequency. In this work, the prototype SSPLL was fabricated in a 65 nm CMOS, and it used the 50 MHz
$f_{\mathbf {REF}}$
. In the measurements, the FDC loop that consumed only 150
$\mu \text{W}$
of power made the SSPLL achieve the lock-in range of 160 MHz and the frequency-reacquisition time of less than 800 ns. The measured rms jitter at 13 GHz was 83 fs. The active area was 0.23 mm
²
, and the total power consumption was 7.7 mW.