New aspects in high-level specification, verification, and design of IT protocols

Growing size and complexity of embedded systems, e.g. for telecommunication and multimedia, increases the demand for efficient, reliable, and comprehensive tools for support of the design process. Formal specification and verification at system level is the way a designer can keep track of a design. This paper tackles the problem to translate a formal specification into a behavioral VHDL model. Prerequisite is a design methodology applying synthesis tools like, e.g. SYNOPSYS, starting with a formal, verifiable specification in cTLA. The verified specification is converted into a behavioral VHDL simulation model which is input for the high level synthesis. Conversion details are demonstrated on an example of the well known Sliding Window Protocol. Future work aims at overcoming the problem to specify, a design in cTLA by using a restricted set of UML.