Transient IR voltage drops in CMOS-based power distribution networks

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient IR voltage drops within a power distribution network. Analytical expressions characterizing these transient IR voltage drops are presented in this paper. The peak value of the transient IR voltage drops based on the analytical expressions is within 6% as compared to SPICE. Circuit- and layout-level design constraints to manage the peak value of the transient IR voltage drops are also discussed.