FPGA Implementation Radix-2 DIT FFT Using Fixed Point Arithmetic and Reduced Arithmetic Complexity

FFT core is very important in many of the digital signal processing systems. They are also used in audio, video and telecommunication applications. FFT core is required to process the Orthogonal Frequency Division Multiplexing function in advanced communication systems. The FFT processors have greatest influence on the development of engineering. In this paper Radix-2 Decimation in Time Fast Fourier Transform is designed, implemented on Spartan-6 FPGA and tested for various input values. Reducing the multiplication count, proposed FFT becomes computationally efficient than the standard Radix-2 FFT. Normalizing the twiddle factors accordingly, complex multiplications present in FFT butterfly architecture are replaced by the combination of simple multipliers and adders. This reduces the area requirements and increase overall operating frequency. In this project we have designed Radix-2 DIT-FFT using 16-bit of data width. The fixed point arithmetic is used so that we can reduce the complexity of the architecture. Overall, the advantage of using improved radix-2 DIT-FFT is reduction of multiplication count by 16.68parcent and the flip flop count by 6.68parcent. It reduces the multiplier count without losing any numerical accuracy.