Reconfigurable Many-Core Embedded Computing Platform with Geometrical Bus Interconnection

There is an increasing interest in many-core embedded system of the scale of hundreds designed specifically with high degree of parallelism. These systems require high performance interconnection with minimum cost. In this paper, we propose a reconfigurable architecture based on a Geometrical Reduced Bus System (GRBS) interconnection and present interconnect characterization in terms of cost, fault tolerance and effective memory bandwidth. GRBS has b number of reduced buses given by ${\text{b}} = \frac{{{\mathbf{min}}\left( {{\mathbf{n}},{\mathbf{m}}} \right)}}{{\mathbf{k}}}$ where n is the number of processor cores and m is number of memory modules and k is the bus reduction factor for number of buses. We present geometrical connections such as rhombic, trapezoidal, cyclic, balanced, staircase and pyramid to connect to either processor cores or memory modules. Our results show that by using reduced bus connections, we can achieve comparable memory bandwidth and 1.5x bandwidth per cost. GRBS provides sustainable memory bandwidth for single bus failure.