A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS

This paper discusses a 56-Gb/s PAM4 receiver analog-front end (AFE) implemented in TSMC 40-nm CMOS process. The system consists of a differential 100- Ω termination, a two-stage continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. The source-degenerated transconductance stage and inverter-based transimpedance (TIA) with source follower structure are adopted for both CTLE and VGA. The utilization of source follower can solve the harsh DC operation problem in conventional inverter-based TIA and extend the bandwidth. By altering the source-degenerated resistors and capacitors in the two-stage CTLE, the proposed AFE can reach fixed peaking frequency with 9-dB compensation range at high frequency. Moreover, it can also achieve a fixed bandwidth at 14 GHz and 9.5-dB DC gain tuning range when altering the feedback resistors and negative capacitance compensation network (NCC) in VGA. Measurement results demonstrate that: it can compensate for 7.3-dB channel loss at 14-GHz Nyquist frequency and open the closed eye for 56-Gb/s PAM4 signal with BER <; 10
^-8
from 2
¹⁵
- 1 PRBS input. The core of the AFE occupies 0.32-mm
²
area and consumes 30-mW power from 1.1/1.2-V supply.