A pipeline of associative memory boards for track finding

We present a pipeline of associative memory boards for track finding, which satisfies the requirements of level two triggers of the next Large Hadron Collider experiments. With respect to previous realizations, the pipelined architecture warrants full scalability of the memory bank, increased bandwidth (by one order of magnitude), and increased number of detector layers (by a factor of two). Each associative memory board consists of four smaller boards, each containing 32 programmable associative memory chips, implemented with a low-cost commercial field-programmable gate array (FPGA). FPGA programming has been optimized for maximum efficiency in terms of pattern density, while printed circuitboard design has been optimized in terms of modularity and FPGA chip density. A complete associative memory board has been successfully tested at 40 MHz; it can contain 7.2/spl times/10/sup 3/ particle trajectories.