Mitigation of Single Event Latchup in High-density SRAMs

Due to the continuous transistor scaling, one of the most important parameters of radiation-tolerant CMOS VLSI circuit design is its resistance to single event latchup (SEL) effects. One of the possible solutions to the problem is to use SOI technology; however, significantly higher SOI substrate costs in comparison with bulk CMOS wafers are the primary barrier. Advantages and disadvantages of known techniques of increasing the radiation tolerance of bulk CMOS technology are considered. In this work TCAD simulation is used to investigate and harden SEL occurring in 90 nm SRAM cells. Experimental data confirm the efficiency and adequacy of the designed model. The memory cell design that provides the required high level of radiation tolerance while minimizing the device occupied area is proposed.