Optimization of the Dual-Technology Back-Enhanced Field Effect Transistor

In this paper we optimize the Dual-Technology Back-Enhanced SOI (DT BESOI) FETs varying the thickness of gate oxide, silicon film and buried oxide focusing on transfer characteristics. The DT BESOI optimization takes into account its behavior as both nMOS and pTunnel-FET device, which are obtained through the variation of positive and negative back biases. In the studied range, the optimized results were t
_ox
=1nm, t
_si
= 10nm and t
_BOX
= 20nm. These DT BESOI results are compared with the conventional nMOS and pTFET devices.