An Input Frequency Insensitive Minimalism SAR with Semi-Synchronous Logic for Time-Interleaving Applications

This paper presents a 1b/cycle, 100-MS/s, 10-b, minimalism single-channel SAR ADC, featured with a 400-MHz effective resolution bandwidth (ERBW), which facilitates it to be embedded into time-interleaved applications. The limited rising time of tracking signal and signal-dependent non-linearity issues have been addressed by an improved bootstrap circuit for the input switch. To enhance the conversion speed, the SAR logic operates in a semi-synchronous mechanism, eliminating the logic delay time from the critical path. The prototype ADC has been designed in 130-nm CMOS process. At 100MS/s and 50-MHz Nyquist input, the SNDR/SFDR are 59.4/62.1-dB. While at 400-MHz input, it still remains 56.4/59.1-dB, showing a good immunity to the input frequency variation. The ADC core occupies an area of 116 µm × 200 µm and consumes 1.3-mW from a 1.2 V supply at Nyquist, resulting a Walden FoM of 17 fJ/conversion-step.