Multi-Core Gateway Architecture and Scheduling Algorithm for High-Performance Gateway Implementation

As the functions of vehicles continue to diversify, the performances of the corresponding electronic control units (ECUs) are being significantly improved. Moreover, the communication speed and data size are also increasing. This can lead to a burden on the gateway, thereby causing problems to the gateway. Therefore, as the number of ECUs and communication performance increase, the performance of the gateway must also increase. In this paper, we propose a multi-core gateway, an operational algorithm, and a new scheduling algorithm for efficient data transfer. In addition, we confirmed that the proposed algorithm could address the problems in existing algorithms (FIFO, SP, and EDF) through comparison.