Two fast architectures for the direct 2-D discrete wavelet transform

We propose two architectures for the direct two-dimensional (2-D) discrete wavelet transform (DWT). The first one is based on a modified recursive pyramid algorithm (MRPA) and performs a ""nonstandard" decomposition (i.e., Mallat's (1989) tree) of an N/spl times/N image in approximately 2N/sup 2//3 clock cycles (ccs). This result consistently speeds up other known architectures that commonly need approximately N/sup 2/ ccs. Furthermore, the proposed architecture is simpler than others in terms of hardware complexity. Subsequently, we show how "symmetric"/"anti-symmetric" properties of linear-phase wavelet filter bases can be exploited in order to further reduce the VLSI area. This is used to design a second architecture that provides one processing unit for each level of decomposition (pipelined approach) and performs a decomposition in approximately N/sup 2//2 ccs. In many practical cases, even this architecture is simpler than general MRPA-based devices (having only one processing unit).