A study of formation and failure mechanism of CMP scratch induced defects on ILD in a W-damascene interconnect SRAM cell

In this study, we investigated the reliability failure mechanism of CMP induced defects in SRAM. A high temperature operating life (HTOL) accelerated test was performed to examine the long-term reliability. It was found that the CMP scratches could cause not only an initial failure but also a fatal long-term reliability failure. The failure mechanism is similar to time dependent dielectric breakdown. The defects result in single bit failures during the accelerated test by node-to-node shorting or node-to-power line shorting in SRAM cells. These defects could not be screened without a very large electric field stress like oxide failure. Novel CMP scratch free W-damascene technology was developed to eliminate the potential defects completely during the fabrication process. It was applied to 8 Mbit low power SRAM products and improved the reliability dramatically.