Design and Analysis of a Low PSIJ, Energy Efficient Bootstrapped Driver for Space Application

The paper presents power supply induced jitter (PSIJ) analysis of a latch based differential CMOS bootstrapped driver, designed for radiation hard particle detection application. The energy efficient driver circuit consists of bootstrap capacitor, boosted node voltages and reduced number of transistors to enhance the gate voltage for better driving efficiency. The closed-form transfer function of the design is derived to analyse the PSIJ. The circuit has been designed in a 180 nm silicon-on-insulator (SOI) technology for its inherent radiation hard by design (RHBD) characteristics with V
DD
of 0.9 V and input frequency of 40 MHz. The worst case PSIJ of the driver circuit is 1.65 ps with ±10% of supply fluctuations. The mathematical model for the design shows a good matching with the simulation and exhibits 13% of mean percentage error (MPE).