0.25pA/Bit Ultra-Low-Leakage 6T Single-Port SRAM on 22nm Bulk Process for IoT Applications

In this paper, we propose a power gating scheme for SRAM in latest bulk technology node for IoT applications. The scheme targets reduction of leakage of both the SRAM cell and the periphery logic. The deep sleep mode memory instance leakage power at TT/0.8V/25°C improves by 100× with respect to standby mode and 25× with respect to the conventional power gating schemes. We are able to achieve 0.25pA/bit of leakage in deep sleep mode. We also propose a leakage sensor-based scheme to reduce the retention mode leakage by 36% at high temperatures.