A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor

A proactive clock-gating system (PCGS) in a 7nm Qualcomm̅ Hexagon™ digital signal processor (DSP) predicts supply voltage (V
_DD
) droops based on microarchitectural events and a power-delivery-network (PDN) model and adapts clock frequency (F
_CLK
) to reduce the V
_DD
droop. Silicon measurements demonstrate 10% higher F
_CLK
or 5% lower V
_DD
.