Logic Block Level Design-Technology Co-Optimization is the New Moore's Law (Invited)

Over the last several technology generations the slower feature scaling has been increasingly complemented by DTCO. Initially, DTCO was employed at a smaller scale to decide which technology modules to introduce to achieve target PPAC (Power-Performance-Area-Cost) specs. Then it was extended to evaluate and optimize a combination of design rules and logic library cell design. Now, DTCO is being extended to cover logic block PPAC for a variety of specific target applications ranging from high performance computing to low power mobile chips. In this talk, we focus on the latest trends in logic block level PPAC analysis and highlight several key components of such analysis that are necessary to achieve the required accuracy at the early pre-silicon DTCO stages.